The present disclosure relates generally to semiconductor device insulating layers and, more specifically, to an insulating layer having a decreased dielectric constant and an increased hardness.
Semiconductor device geometries continue to dramatically decrease in size. For example, existing semiconductor devices routinely include features having dimensions less than 90 nm. A challenge that has become ever more difficult as this scaling continues has been decreasing interconnect RC time constant delay. Those skilled in the art understand that power dissipation due to resistance-capacitance (RC) coupling becomes significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metallization level. Smaller line dimensions increase the resistivity of the metal lines and the narrow spacing between the metal lines increases the resulting capacitance. Thus, device speed will increase as dimensions of ultralarge-scale integration devices scale to smaller feature sizes (<0.25 μm).
However, the capacitance between interconnect lines is proportional to the dielectric constant k of the insulating material between the lines. Thus, a reduction in k leads to lower capacitance and a decreased RC delay. Moreover, when the separation between interconnect lines is less than 0.3 μm, the interlayer capacitance is very small compared to the total capacitance. Thus, at sub-0.25 μm feature sizes, as much as 90% of the total capacitance is dominated by line-to-line capacitance. Consequently, a reduction in line-to-line capacitance is one of the most critical issues for sub-0.25 μm devices. An additional advantage in reducing the total capacitance is that it decreases the power dissipation and crosstalk.
However, low-k materials can exhibit a high porosity and low density, such that insulating layers comprising conventional low-k materials typically provide a film having insufficient hardness and excessive film stress. Consequently, a stack of low-k dielectric films can suffer internal stress, due at least in part to lattice mismatches between over-stressed layers. Moreover, such stress may intensify or build up during conventional fabrication procedures requiring substantial application forces and thermal cycling. As a result, the low-k insulating layers may crack or peel, which can increase dielectric constants and decrease hardness values.
Previous attempts to address the problems discussed above include post treatment thermal annealing and H2 or NH3 plasma treatment to increase the film hardness and to help reduce moisture absorption by the low-k dielectric. However, these processes provide only modest improvement in dielectric constants and insufficiently address on-going issues with excessive stress and insufficient mechanical stability. For example, insulating layers undergoing such post treatment still experience dishing, cracking, pitting and peeling during chemical-mechanical polishing (CMP), and are highly susceptible to copper or other conductive material diffusion even after being annealed.
Therefore, what is needed in the art is an insulating layer and method of manufacture thereof that addresses the problems discussed above.